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When quoting this document, please refer to the following
DOI: 10.4230/OASIcs.WCET.2007.1189
URN: urn:nbn:de:0030-drops-11891
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Schlickling, Marc ; Pister, Markus

A Framework for Static Analysis of VHDL Code

schlickling.1189.pdf (0.1 MB)


Software in real time systems underlies strict timing constraints.
These are among others hard deadlines regarding
the worst-case execution time (WCET) of the application.
Thus, the computation of a safe and precise WCET is a key
issue1 for validating the behavior of safety-critical systems,
e.g. the flight control system in avionics or the airbag control
software in the automotive industry.
Saarland University and AbsInt Angewandte Informatik
GmbH have developed a successful approach for computing
the WCET of a task. The resulting tool, called aiT, is
based on the abstract interpretation [3, 4] of timing models
of the processor and its periphery. Such timing models
are hand-crafted and therefore error-prone. Additionally
the modeling requires a hard engineering effort, so that the
development process is very time consuming.
Because modern processors are synthesized from a formal
hardware specification, e.g., in VHDL or VERILOG, the
hand-crafted timing model can be developed by manually
analyzing the processor specification.
Due to the complexity of this step, there is a need for support
tools that ease the creation of analyzes on such specifi-
cations. This paper introduces the primer work on a framework
for static analyzes on VHDL.

BibTeX - Entry

  author =	{Marc Schlickling and Markus Pister},
  title =	{{A Framework for Static Analysis of VHDL Code}},
  booktitle =	{7th International Workshop on Worst-Case Execution Time Analysis (WCET'07)},
  series =	{OpenAccess Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-05-7},
  ISSN =	{2190-6807},
  year =	{2007},
  volume =	{6},
  editor =	{Christine Rochange},
  publisher =	{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{},
  URN =		{urn:nbn:de:0030-drops-11891},
  doi =		{10.4230/OASIcs.WCET.2007.1189},
  annote =	{Keywords: Timing Analysis, Worst-Case Execution Time, VHDL, Static Analysis}

Keywords: Timing Analysis, Worst-Case Execution Time, VHDL, Static Analysis
Collection: 7th International Workshop on Worst-Case Execution Time Analysis (WCET'07)
Issue Date: 2007
Date of publication: 13.11.2007

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