The beta version of DROPS 2 is now publicly available! Check this page out at DROPS 2 now!


License: Creative Commons Attribution 3.0 Unported license (CC BY 3.0)
When quoting this document, please refer to the following
DOI: 10.4230/LIPIcs.ECRTS.2020.13
URN: urn:nbn:de:0030-drops-123764
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2020/12376/
Go to the corresponding LIPIcs Volume Portal

Sensfelder, Nathanaël ; Brunel, Julien ; Pagetti, Claire

On How to Identify Cache Coherence: Case of the NXP QorIQ T4240

pdf-format:
LIPIcs-ECRTS-2020-13.pdf (0.8 MB)

Abstract

Architectures used in safety critical systems have to pass certain certification standards, which require sufficient proof that they will behave as expected. Multi-core processors make this challenging by featuring complex interactions between the tasks they run. A lot of these interactions are made without explicit instructions from the program designers. Furthermore, they can have strong negative impacts on performance (and potentially affect correctness). One important such source of interactions is cache coherence, which speeds up operations in most cases, but can also lead to unexpected variations in execution time if not fully understood. Architecture documentations often lack details on the implementation of cache coherence. We thus propose a strategy to ascertain that the platform does indeed implement the cache coherence protocol its user believes it to. We also apply this strategy to the NXP QorIQ T4240, resulting in the identification of a protocol (MESIF) other than the one this architecture’s documentation led us to believe it was using (MESI).

BibTeX - Entry

@InProceedings{sensfelder_et_al:LIPIcs:2020:12376,
  author =	{Nathana{\"e}l Sensfelder and Julien Brunel and Claire Pagetti},
  title =	{{On How to Identify Cache Coherence: Case of the NXP QorIQ T4240}},
  booktitle =	{32nd Euromicro Conference on Real-Time Systems (ECRTS 2020)},
  pages =	{13:1--13:22},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-152-8},
  ISSN =	{1868-8969},
  year =	{2020},
  volume =	{165},
  editor =	{Marcus V{\"o}lp},
  publisher =	{Schloss Dagstuhl--Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/opus/volltexte/2020/12376},
  URN =		{urn:nbn:de:0030-drops-123764},
  doi =		{10.4230/LIPIcs.ECRTS.2020.13},
  annote =	{Keywords: Real-time systems, multi-core processor, cache coherence}
}

Keywords: Real-time systems, multi-core processor, cache coherence
Collection: 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020)
Issue Date: 2020
Date of publication: 30.06.2020

DROPS-Home | Fulltext Search | Imprint | Privacy Published by LZI