License:
Creative Commons Attribution 4.0 International license (CC BY 4.0)
When quoting this document, please refer to the following
DOI: 10.4230/LIPIcs.ECRTS.2021.2
URN: urn:nbn:de:0030-drops-139331
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2021/13933/
Hoornaert, Denis ;
Roozkhosh, Shahin ;
Mancuso, Renato
A Memory Scheduling Infrastructure for Multi-Core Systems with Re-Programmable Logic
Abstract
The sharp increase in demand for performance has prompted an explosion in the complexity of modern multi-core embedded systems. This has lead to unprecedented temporal unpredictability concerns in Cyber-Physical Systems (CPS). On-chip integration of programmable logic (PL) alongside a conventional Processing System (PS) in modern Systems-on-Chip (SoC) establishes a genuine compromise between specialization, performance, and reconfigurability. In addition to typical use-cases, it has been shown that the PL can be used to observe, manipulate, and ultimately manage memory traffic generated by a traditional multi-core processor.
This paper explores the possibility of PL-aided memory scheduling by proposing a Scheduler In-the-Middle (SchIM). We demonstrate that the SchIM enables transaction-level control over the main memory traffic generated by a set of embedded cores. Focusing on extensibility and reconfigurability, we put forward a SchIM design covering two main objectives. First, to provide a safe playground to test innovative memory scheduling mechanisms; and second, to establish a transition path from software-based memory regulation to provably correct hardware-enforced memory scheduling. We evaluate our design through a full-system implementation on a commercial PS-PL platform using synthetic and real-world benchmarks.
BibTeX - Entry
@InProceedings{hoornaert_et_al:LIPIcs.ECRTS.2021.2,
author = {Hoornaert, Denis and Roozkhosh, Shahin and Mancuso, Renato},
title = {{A Memory Scheduling Infrastructure for Multi-Core Systems with Re-Programmable Logic}},
booktitle = {33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)},
pages = {2:1--2:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-192-4},
ISSN = {1868-8969},
year = {2021},
volume = {196},
editor = {Brandenburg, Bj\"{o}rn B.},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/opus/volltexte/2021/13933},
URN = {urn:nbn:de:0030-drops-139331},
doi = {10.4230/LIPIcs.ECRTS.2021.2},
annote = {Keywords: Memory Scheduling, PLIM, FPGA, Memory Management, Bandwidth Regulation, MemGuard, Coloring, Bank Partitioning, Real-time, Multicore, Safety-critical}
}
Keywords: |
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Memory Scheduling, PLIM, FPGA, Memory Management, Bandwidth Regulation, MemGuard, Coloring, Bank Partitioning, Real-time, Multicore, Safety-critical |
Collection: |
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33rd Euromicro Conference on Real-Time Systems (ECRTS 2021) |
Issue Date: |
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2021 |
Date of publication: |
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30.06.2021 |
Supplementary Material: |
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The SchIM sources are available at Software: https://github.com/denishoornaert/MemorEDF |