License: Creative Commons Attribution 4.0 International license (CC BY 4.0)
When quoting this document, please refer to the following
DOI: 10.4230/DagSemProc.08081.3
URN: urn:nbn:de:0030-drops-15315
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2008/1531/
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Lopez-Ortiz, Alejandro ; Dorrigiv, Reza ; Salinger, Alejandro

Optimal Speedup on a Low-Degree Multi-Core Parallel Architecture (LoPRAM)

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Abstract

We propose a new model with small degreee of parallelism that reflects current and future multicore architectures in practice. The model is based on the PRAM architecture and hence it inherits many of its interesting theoretical properties. The key observations and differences are that the degree of parallelism (i.e. number of processors or cores) is bounded by O(log n), the synchronization model is looser and the use of parallelism is at a higher level unless explicitly specified otherwise. Surprisingly, these three rather minor variants result in a model in which obtaining work optimal algorithms is significantly easier than for the PRAM.

The new model is called Low-degree PRAM or LoPRAM for short. Lastly we observe that there are thresholds in complexity of programming at p=O(log n) and p=O(sqrt(n)) and provide references for specific problems for which this threshold has been formally proven.

BibTeX - Entry

@InProceedings{lopezortiz_et_al:DagSemProc.08081.3,
  author =	{Lopez-Ortiz, Alejandro and Dorrigiv, Reza and Salinger, Alejandro},
  title =	{{Optimal Speedup on a Low-Degree Multi-Core Parallel Architecture (LoPRAM)}},
  booktitle =	{Data Structures},
  pages =	{1--13},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2008},
  volume =	{8081},
  editor =	{Lars Arge and Robert Sedgewick and Raimund Seidel},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/opus/volltexte/2008/1531},
  URN =		{urn:nbn:de:0030-drops-15315},
  doi =		{10.4230/DagSemProc.08081.3},
  annote =	{Keywords: PRAM, multicore architectures, parallelism, algorithms, dynamic programming, divide and conquer}
}

Keywords: PRAM, multicore architectures, parallelism, algorithms, dynamic programming, divide and conquer
Collection: 08081 - Data Structures
Issue Date: 2008
Date of publication: 16.06.2008

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