License: Creative Commons Attribution 4.0 International license (CC BY 4.0)
When quoting this document, please refer to the following
DOI: 10.4230/OASIcs.PARMA-DITAM.2022.2
URN: urn:nbn:de:0030-drops-161186
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2022/16118/
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Zamacola, Rafael ; Otero, Andrés ; Rodríguez, Alfonso ; de la Torre, Eduardo

Just-In-Time Composition of Reconfigurable Overlays (Invited Talk)

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OASIcs-PARMA-DITAM-2022-2.pdf (4 MB)

Abstract

This paper describes a framework supporting the automatic composition of reconfigurable overlays laid on top of an FPGA to offload computing-intensive sections of a given application, from an embedded processor to a loosely coupled reconfigurable accelerator. Overlays provide an abstraction layer acting as an intermediate fabric between users' applications and the FPGA fabric. Among the existing flavors, the overlay template proposed in this work is based on a coarse-grain reconfigurable architecture featuring word-level operators, reducing long place-and-route times associated with FPGA designs. The proposed overlays are composed at run-time using a tile-based approach, in which pre-synthesized processing elements are stitched together following a 2D grid pattern and using dynamic and partial reconfiguration. The proposed reconfigurable architecture is accompanied by an automated toolchain that, relying on an LLVM intermediate representation, automatically converts the source code to a data-flow graph that is afterward mapped onto the overlay. A mapping example is provided in this paper to show the possibilities enabled by the framework, including loop mapping and loop unrolling support, features originally described in this work.

BibTeX - Entry

@InProceedings{zamacola_et_al:OASIcs.PARMA-DITAM.2022.2,
  author =	{Zamacola, Rafael and Otero, Andr\'{e}s and Rodr{\'\i}guez, Alfonso and de la Torre, Eduardo},
  title =	{{Just-In-Time Composition of Reconfigurable Overlays}},
  booktitle =	{13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2022)},
  pages =	{2:1--2:13},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-231-0},
  ISSN =	{2190-6807},
  year =	{2022},
  volume =	{100},
  editor =	{Palumbo, Francesca and Bispo, Jo\~{a}o and Cherubin, Stefano},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/opus/volltexte/2022/16118},
  URN =		{urn:nbn:de:0030-drops-161186},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2022.2},
  annote =	{Keywords: FPGA, Dynamic Partial Reconfiguration, Overlay, LLVM, Compilation}
}

Keywords: FPGA, Dynamic Partial Reconfiguration, Overlay, LLVM, Compilation
Collection: 13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2022)
Issue Date: 2022
Date of publication: 08.06.2022

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