License: Creative Commons Attribution 4.0 International license (CC BY 4.0)
When quoting this document, please refer to the following
DOI: 10.4230/LIPIcs.ECRTS.2022.16
URN: urn:nbn:de:0030-drops-163330
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2022/16333/
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Mirosanlou, Reza ; Hassan, Mohamed ; Pellizzoni, Rodolfo

Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds

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LIPIcs-ECRTS-2022-16.pdf (2 MB)

Abstract

In Commercial-Off-The-Shelf (COTS) systems-on-chip, processing elements communicate data through a shared memory hierarchy, and a coherent high-performance interconnect, where the de facto standard to handle shared data is through a coherence protocol. Driven by the extraordinary demands from modern real-time embedded system applications to generate, process, and communicate massive amounts of data, recent efforts aim to ensure timing predictability while integrating cache coherence in multi-core real-time systems. However, we observe that most of these efforts compromise system average performance upon offering predictability guarantees. Motivated by this observation, this work proposes an arbiter aimed at providing a predictable, coherent shared cache hierarchy solution, yet with a negligible performance degradation compared to COTS solutions. We achieve this goal by adopting a high-performance-driven architecture including a split-transaction bus and bankized shared cache. In addition, all accesses are arbitrated through a global ordering mechanism. Our proposed arbiter operates alongside conventional coherence protocols without requiring any protocol modifications. Furthermore, we leverage the Duetto reference model by pairing the proposed arbiter and a high-performance arbiter. We evaluate our solution based on both synthetic and SPLASH-3 benchmarks, showing that we can significantly outperform the state-of-the-art in predictable cache coherence, while offering a COTS-level performance.

BibTeX - Entry

@InProceedings{mirosanlou_et_al:LIPIcs.ECRTS.2022.16,
  author =	{Mirosanlou, Reza and Hassan, Mohamed and Pellizzoni, Rodolfo},
  title =	{{Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds}},
  booktitle =	{34th Euromicro Conference on Real-Time Systems (ECRTS 2022)},
  pages =	{16:1--16:27},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-239-6},
  ISSN =	{1868-8969},
  year =	{2022},
  volume =	{231},
  editor =	{Maggio, Martina},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/opus/volltexte/2022/16333},
  URN =		{urn:nbn:de:0030-drops-163330},
  doi =		{10.4230/LIPIcs.ECRTS.2022.16},
  annote =	{Keywords: Predictability, Cache, COTS, Arbitration, Real-time system}
}

Keywords: Predictability, Cache, COTS, Arbitration, Real-time system
Collection: 34th Euromicro Conference on Real-Time Systems (ECRTS 2022)
Issue Date: 2022
Date of publication: 28.06.2022

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