License: 
Creative Commons Attribution 4.0 International license (CC BY 4.0)
When quoting this document, please refer to the following
DOI: 10.4230/OASIcs.PARMA-DITAM.2023.6
URN: urn:nbn:de:0030-drops-177268
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2023/17726/
Piccoli, Michele ;
Zoni, Davide ;
Fornaciari, William ;
Massari, Giuseppe ;
Cococcioni, Marco ;
Rossi, Federico ;
Saponara, Sergio ;
Ruffaldi, Emanuele
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments
Abstract
Since its introduction in 2017, the Posit™ format for representing real numbers has attracted a lot of interest, as an alternative to IEEE 754 floating point representation. Several hardware implementations of arithmetic operations between posit numbers have also been proposed in recent years. In this work, we analyze the dynamic power consumption of the Full Posit Processing Unit (FPPU) recently developed at the University of Pisa. Experimental results show that we can model the dynamic power consumption of the FPPU with an acceptable approximation error from 2.84% (32-bit FPPU) to 7.32% (8-bit FPPU). Furthermore, from the synthesis of the power monitoring unit alongside the FPPU we demonstrate that the additional power module has an area cost that goes from ∼5% (32-bit FPPU) to ∼30% (8-bit FPPU) of the total unit area occupation.
BibTeX - Entry
@InProceedings{piccoli_et_al:OASIcs.PARMA-DITAM.2023.6,
author = {Piccoli, Michele and Zoni, Davide and Fornaciari, William and Massari, Giuseppe and Cococcioni, Marco and Rossi, Federico and Saponara, Sergio and Ruffaldi, Emanuele},
title = {{Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
pages = {6:1--6:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-269-3},
ISSN = {2190-6807},
year = {2023},
volume = {107},
editor = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/opus/volltexte/2023/17726},
URN = {urn:nbn:de:0030-drops-177268},
doi = {10.4230/OASIcs.PARMA-DITAM.2023.6},
annote = {Keywords: power estimation, computer arithmetic, posit numbers}
}
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Keywords: |
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power estimation, computer arithmetic, posit numbers |
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Collection: |
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14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023) |
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Issue Date: |
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2023 |
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Date of publication: |
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13.03.2023 |
