License: Creative Commons Attribution 4.0 International license (CC BY 4.0)
When quoting this document, please refer to the following
DOI: 10.4230/DagSemProc.08371.3
URN: urn:nbn:de:0030-drops-19235
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2009/1923/
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Steininger, Andreas

Error Containment in the Presence of Metastability

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08371.SteiningerAndreas.Paper.1923.pdf (0.2 MB)

Abstract

Error containment is an important concept in fault tolerant system
design, and techniques like voting are applied to mask erroneous
outputs, thus preventing their propagation. In this presentation
we will use the example of DARTS, a fault-tolerant distributed
clock generation scheme in hardware, to demonstrate that
metastability is a substantial threat to error containment. We
will illustrate how metastability can originate and propagate such
that a single fault may upset the system. The main conclusion is
that modeling efforts on all design levels are definitely required
in order to mitigate and quantify the deteriorating effect of
metastability on system dependability.

BibTeX - Entry

@InProceedings{steininger:DagSemProc.08371.3,
  author =	{Steininger, Andreas},
  title =	{{Error Containment in the Presence of Metastability}},
  booktitle =	{Fault-Tolerant Distributed Algorithms on VLSI Chips},
  pages =	{1--5},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2009},
  volume =	{8371},
  editor =	{Bernadette Charron-Bost and Shlomi Dolev and Jo Ebergen and Ulrich Schmid},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/opus/volltexte/2009/1923},
  URN =		{urn:nbn:de:0030-drops-19235},
  doi =		{10.4230/DagSemProc.08371.3},
  annote =	{Keywords: Metastability, fault tolerance, clock generation}
}

Keywords: Metastability, fault tolerance, clock generation
Collection: 08371 - Fault-Tolerant Distributed Algorithms on VLSI Chips
Issue Date: 2009
Date of publication: 13.03.2009

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