License: Creative Commons Attribution 4.0 International license (CC BY 4.0)
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DOI: 10.4230/DagSemProc.10281.14
URN: urn:nbn:de:0030-drops-28344
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Hredzak, Branislav ; Diessel, Oliver

Towards Dilated Placement of Dynamic NoC Cores

10281.DiesselOliver.Paper.2834.pdf (0.3 MB)


Instead of mapping application task graphs in a compact manner onto
reconfigurable devices using a network-on-chip for interconnecting
application cores, we propose dilating the mappings as much as the
available latencies on critical connections allow. In a dilated mapping,
the unused resources between an application's configured components can
be used to provide additional flexibility when the configuration needs
to change. We motivate the reasons for dilating application task graphs
targeted at reconfigurable devices; derive a simulated annealing approach
to dilating the placement of such graphs; and present preliminary results
of applying the algorithm to synthetic test cases. The method appears to
result in successful and meaningful graph dilation and could be further
tuned to satisfy desired power constraints.

BibTeX - Entry

  author =	{Hredzak, Branislav and Diessel, Oliver},
  title =	{{Towards Dilated Placement of Dynamic NoC Cores}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--18},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{},
  URN =		{urn:nbn:de:0030-drops-28344},
  doi =		{10.4230/DagSemProc.10281.14},
  annote =	{Keywords: Modular reconfiguration, networks-on-chip, application mapping, dilation}

Keywords: Modular reconfiguration, networks-on-chip, application mapping, dilation
Collection: 10281 - Dynamically Reconfigurable Architectures
Issue Date: 2010
Date of publication: 14.12.2010

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