License: Creative Commons Attribution 4.0 International license (CC BY 4.0)
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DOI: 10.4230/DagSemProc.10281.6
URN: urn:nbn:de:0030-drops-28389
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Huthmann, Jens ; Müller, Peter ; Stock, Florian ; Hildenbrand, Dietmar ; Koch, Andreas

Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators

10281.KochAndreas.Paper.2838.pdf (0.4 MB)


Geometric Algebra (GA), a generalization of quaternions and complex numbers, is a very
powerful framework for intuitively expressing and manipulating the complex
geometric relationships common to engineering problems.
However, actual processing of GA expressions is very compute intensive, and
acceleration is generally required for practical use. GPUs and FPGAs offer
such acceleration, while requiring only low-power per operation.
In this paper, we present key components of a proof-of-concept compile flow
combining symbolic and hardware optimization techniques to
automatically generate hardware accelerators from the abstract GA descriptions that are suitable for high-performance embedded computing.

BibTeX - Entry

  author =	{Huthmann, Jens and M\"{u}ller, Peter and Stock, Florian and Hildenbrand, Dietmar and Koch, Andreas},
  title =	{{Compiling Geometric Algebra Computations into Reconfigurable  Hardware Accelerators}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--15},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{},
  URN =		{urn:nbn:de:0030-drops-28389},
  doi =		{10.4230/DagSemProc.10281.6},
  annote =	{Keywords: Geometric Algebra FPGA High-Level-Compiler Gaalop}

Keywords: Geometric Algebra FPGA High-Level-Compiler Gaalop
Collection: 10281 - Dynamically Reconfigurable Architectures
Issue Date: 2010
Date of publication: 14.12.2010

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