Abstract
Scaling technology enables even higher degree of integration for FPGAs, but also brings new challenges that need to be addressed from both the architecture and the design tools side. Optimization of FPGA interconnection network is essential, given that interconnects dominate logic. Two approaches are presented, with one based on the time-multiplexing of wires and the other using hierarchical interconnects of high-speed serial links and switches. Design tools for both approaches are discussed. Preliminary experiments and prototypes are presented, and show positive results.
BibTeX - Entry
@InProceedings{chen_et_al:DagSemProc.10281.12,
author = {Chen, Xiaolei and Ha, Yajun},
title = {{The Optimization of Interconnection Networks in FPGAs}},
booktitle = {Dynamically Reconfigurable Architectures},
pages = {1--9},
series = {Dagstuhl Seminar Proceedings (DagSemProc)},
ISSN = {1862-4405},
year = {2010},
volume = {10281},
editor = {Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/opus/volltexte/2010/2842},
URN = {urn:nbn:de:0030-drops-28425},
doi = {10.4230/DagSemProc.10281.12},
annote = {Keywords: Field-programmable gate array, architecture, computer-aided design}
}
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Keywords: |
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Field-programmable gate array, architecture, computer-aided design |
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Collection: |
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10281 - Dynamically Reconfigurable Architectures |
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Issue Date: |
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2010 |
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Date of publication: |
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14.12.2010 |
Creative Commons Attribution 4.0 International license (CC BY 4.0)