License: 
Creative Commons Attribution 3.0 Unported license (CC BY 3.0)
When quoting this document, please refer to the following
DOI: 10.4230/OASIcs.ICCSW.2013.136
URN: urn:nbn:de:0030-drops-42825
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2013/4282/
Zaidi, Ali Mustafa ;
Greaves, David J.
Achieving Superscalar Performance without Superscalar Overheads - A Dataflow Compiler IR for Custom Computing
Abstract
The difficulty of effectively parallelizing code for multicore processors, combined with the end of threshold voltage scaling has resulted in the problem of 'Dark Silicon', severely limiting performance scaling despite Moore's Law. To address dark silicon, not only must we drastically improve the energy efficiency of computation, but due to Amdahl's Law, we must do so without compromising sequential performance. Designers increasingly utilize custom hardware to dramatically improve both efficiency and performance in increasingly heterogeneous architectures. Unfortunately, while it efficiently accelerates numeric, data-parallel applications, custom hardware often exhibits poor performance on sequential code, so complex, power-hungry superscalar processors must still be utilized. This paper addresses the problem of improving sequential performance in custom hardware by (a) switching from a statically scheduled to a dynamically scheduled (dataflow) execution model, and (b) developing a new compiler IR for high-level synthesis that enables aggressive exposition of ILP even in the presence of complex control flow. This new IR is directly implemented as a static dataflow graph in hardware by our high-level synthesis tool-chain, and shows an average speedup of 1.13 times over equivalent hardware generated using LegUp, an existing HLS tool. In addition, our new IR allows us to further trade area & energy for performance, increasing the average speedup to 1.55 times, through loop unrolling, with a peak speedup of 4.05 times. Our custom hardware is able to approach the sequential cycle-counts of an Intel Nehalem Core i7 superscalar processor, while consuming on average only 0.25 times the energy of an in-order Altera Nios IIf processor.
BibTeX - Entry
@InProceedings{zaidi_et_al:OASIcs:2013:4282,
author = {Ali Mustafa Zaidi and David J. Greaves},
title = {{Achieving Superscalar Performance without Superscalar Overheads - A Dataflow Compiler IR for Custom Computing}},
booktitle = {2013 Imperial College Computing Student Workshop},
pages = {136--143},
series = {OpenAccess Series in Informatics (OASIcs)},
ISBN = {978-3-939897-63-7},
ISSN = {2190-6807},
year = {2013},
volume = {35},
editor = {Andrew V. Jones and Nicholas Ng},
publisher = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
address = {Dagstuhl, Germany},
URL = {http://drops.dagstuhl.de/opus/volltexte/2013/4282},
URN = {urn:nbn:de:0030-drops-42825},
doi = {10.4230/OASIcs.ICCSW.2013.136},
annote = {Keywords: High-level Synthesis, Instruction Level Parallelism, Custom Computing, Compilers, Dark Silicon}
}
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Keywords: |
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High-level Synthesis, Instruction Level Parallelism, Custom Computing, Compilers, Dark Silicon |
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Collection: |
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2013 Imperial College Computing Student Workshop |
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Issue Date: |
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2013 |
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Date of publication: |
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14.10.2013 |
