License: Creative Commons Attribution 4.0 International license (CC BY 4.0)
When quoting this document, please refer to the following
DOI: 10.4230/DagSemProc.03471.4
URN: urn:nbn:de:0030-drops-57
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Berg, Christoph ; Engblom, Jakob ; Wilhelm, Reinhard

Requirements for and Design of a Processor with Predictable Timing

03471_christoph_berg_paper.pdf (0.2 MB)


This paper introduces a set of design principles that aim to make processor
architectures amenable to static timing analysis. Based on these principles,
we give a design of a hard real-time processor with predictable timing, which is
simultaneously capable of reaching respectable performance levels.
The design principles we identify are recoverability from information loss in
the analysis, minimal variation of the instruction timing, non-interference between
processor components, deterministic processor behavior, and comprehensive
documentation. The principles are based on our experience and that of other
researchers in building timing analysis tools for existing processors.

BibTeX - Entry

  author =	{Berg, Christoph and Engblom, Jakob and Wilhelm, Reinhard},
  title =	{{Requirements for and Design of a Processor with Predictable Timing}},
  booktitle =	{Perspectives Workshop: Design of Systems with Predictable Behaviour},
  pages =	{1--20},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2004},
  volume =	{3471},
  editor =	{Lothar Thiele and Reinhard Wilhelm},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{},
  URN =		{urn:nbn:de:0030-drops-57},
  doi =		{10.4230/DagSemProc.03471.4},
  annote =	{Keywords: WCET, hard real-time, embedded systems, computer architecture}

Keywords: WCET, hard real-time, embedded systems, computer architecture
Collection: 03471 - Design of Systems with Predictable Behaviour
Issue Date: 2004
Date of publication: 10.09.2004

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