License: Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported license (CC BY-NC-ND 3.0)
When quoting this document, please refer to the following
DOI: 10.4230/OASIcs.WCET.2006.672
URN: urn:nbn:de:0030-drops-6723
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2006/672/
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Berg, Christoph
Timing Anomalies

PLRU Cache Domino Effects

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WCET_Berg.672.pdf (0.03 MB)

Abstract

Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and Stenström, domino effects caused by pipeline stalls were shows to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET. PLRU is used in the PowerPC PPC755, which is widely used in embedded systems, and some x86 models.

BibTeX - Entry

@InProceedings{berg:OASIcs:2006:672,
  author =	{Christoph Berg},
  title =	{{PLRU Cache Domino Effects}},
  booktitle =	{6th International Workshop on Worst-Case Execution Time Analysis (WCET'06)},
  series =	{OpenAccess Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-03-3},
  ISSN =	{2190-6807},
  year =	{2006},
  volume =	{4},
  editor =	{Frank Mueller},
  publisher =	{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{http://drops.dagstuhl.de/opus/volltexte/2006/672},
  URN =		{urn:nbn:de:0030-drops-6723},
  doi =		{10.4230/OASIcs.WCET.2006.672},
  annote =	{Keywords: Embedded systems, predictability, cache memory, PLRU, domino effects, timing anomalies}
}

Keywords: Embedded systems, predictability, cache memory, PLRU, domino effects, timing anomalies
Collection: 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06)
Issue Date: 2006
Date of publication: 23.08.2006

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