License: Creative Commons Attribution 3.0 Unported license (CC BY 3.0)
When quoting this document, please refer to the following
DOI: 10.4230/OASIcs.WCET.2016.12
URN: urn:nbn:de:0030-drops-69051
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2016/6905/
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Löfwenmark, Andreas ; Nadjm-Tehrani, Simin

Understanding Shared Memory Bank Access Interference in Multi-Core Avionics

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OASIcs-WCET-2016-12.pdf (0.4 MB)

Abstract

Deployment of multi-core platforms in safety-critical applications requires reliable estimation of worst-case response time (WCRT) for critical processes. Determination of WCRT needs to accurately estimate and measure the interferences arising from multiple processes and multiple cores. Earlier works have proposed frameworks in which CPU, shared cache, and shared memory (DRAM) interferences can be estimated using some application and platform-dependent parameters. In this work we examine a recent work in which single core equivalent (SCE) worst case execution time is used as a basis for deriving WCRT. We describe the specific requirements in an avionics context including the sharing of memory banks by multiple processes on multiple cores, and adapt the SCE framework to account for them. We present the needed adaptations to a real-time operating system to enforce the requirements, and present a methodology for validating the theoretical WCRT through measurements on the resulting platform. The work reveals that the framework indeed creates a (pessimistic) bound on the WCRT. It also discloses that the maximum interference for memory accesses does not arise when all cores share the same memory bank.

BibTeX - Entry

@InProceedings{lfwenmark_et_al:OASIcs:2016:6905,
  author =	{Andreas L{\"o}fwenmark and Simin Nadjm-Tehrani},
  title =	{{Understanding Shared Memory Bank Access Interference in Multi-Core Avionics}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{12:1--12:11},
  series =	{OpenAccess Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Martin Schoeberl},
  publisher =	{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{http://drops.dagstuhl.de/opus/volltexte/2016/6905},
  URN =		{urn:nbn:de:0030-drops-69051},
  doi =		{10.4230/OASIcs.WCET.2016.12},
  annote =	{Keywords: multi-core, avionics, shared memory systems, WCET}
}

Keywords: multi-core, avionics, shared memory systems, WCET
Collection: 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)
Issue Date: 2016
Date of publication: 20.12.2016

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