License: Creative Commons Attribution 3.0 Unported license (CC BY 3.0)
When quoting this document, please refer to the following
DOI: 10.4230/LIPIcs.ECRTS.2017.6
URN: urn:nbn:de:0030-drops-71543
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2017/7154/
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Lucas, Pierre ; Chappuis, Kevin ; Paolino, Michele ; Dagieu, Nicolas ; Raho, Daniel

VOSYSmonitor, a Low Latency Monitor Layer for Mixed-Criticality Systems on ARMv8-A

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LIPIcs-ECRTS-2017-6.pdf (0.7 MB)

Abstract

With the emergence of multicore embedded System on Chip (SoC), the integration of several applications with different levels of criticality on the same platform is becoming increasingly popular. These platforms, known as mixed-criticality systems, need to meet numerous requirements such as real-time constraints, Operating System (OS) scheduling, memory and OSes isolation.

To construct mixed-criticality systems, various solutions, based on virtualization extensions, have been presented where OSes are contained in a Virtual Machine (VM) through the use of a hypervisor. However, such implementations usually lack hardware features to ensure a full isolation of other bus masters (e.g., Direct Memory Access (DMA) peripherals, Graphics Processing Unit (GPU)) between OSes. Furthermore on multicore implementation, one core is usually dedicated to one OS, causing CPU underutilization.

To address these issues, this paper presents VOSYSmonitor, a multi-core software layer, which allows the co-execution of a safety-critical Real-Time Operating System (RTOS) and a non-critical General Purpose Operating System (GPOS) on the same hardware ARMv8-A platform.
VOSYSmonitor main differentiation factors with the known solutions is the possibility for a processor to switch between secure and non-secure code execution at runtime. The partitioning is ensured by the ARM TrustZone technology, thus allowing to preserve the usage of virtualization features for the GPOS.

VOSYSmonitor architecture will be detailed in this paper, while benchmarking its performance versus other known solutions.

BibTeX - Entry

@InProceedings{lucas_et_al:LIPIcs:2017:7154,
  author =	{Pierre Lucas and Kevin Chappuis and Michele Paolino and Nicolas Dagieu and Daniel Raho},
  title =	{{VOSYSmonitor, a Low Latency Monitor Layer for Mixed-Criticality Systems on ARMv8-A}},
  booktitle =	{29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
  pages =	{6:1--6:18},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-037-8},
  ISSN =	{1868-8969},
  year =	{2017},
  volume =	{76},
  editor =	{Marko Bertogna},
  publisher =	{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{http://drops.dagstuhl.de/opus/volltexte/2017/7154},
  URN =		{urn:nbn:de:0030-drops-71543},
  doi =		{10.4230/LIPIcs.ECRTS.2017.6},
  annote =	{Keywords: VOSYSmonitor, ARM TrustZone, Mixed Criticality, Real Time}
}

Keywords: VOSYSmonitor, ARM TrustZone, Mixed Criticality, Real Time
Collection: 29th Euromicro Conference on Real-Time Systems (ECRTS 2017)
Issue Date: 2017
Date of publication: 23.06.2017

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