License: Creative Commons Attribution 4.0 International license (CC BY 4.0)
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DOI: 10.4230/DagSemProc.06141.12
URN: urn:nbn:de:0030-drops-7410
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Maskell, Douglas ; Oliver, Timothy F.

Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System

06141.MaskellDoug.Paper.741.pdf (0.4 MB)


This paper presents a method of constructing pre-routed FPGA cores. This lays the foundations for a rapid system construction framework. There are two major challenges that need to be considered by this framework. The first is how to manage the wires crossing a core’s borders. The second is how to maintain an acceptable level of flexibility for system construction with only a minimum of overhead. Typical FPGA based systems are built up from cores developed by multiple third parties. Each compilation step that a developer performs before delivery adds value in terms of a cores performance, predictability and readiness for purpose. The perceived advantages of full independent core development are weighed against the loss in placement flexibility and elimination of the opportunities to optimise a system across cores. Few existing methodologies allow the independent compilation of FPGA cores through every step of the design flow. The wire detail of modern FPGA architectures is captured in a model that is used to analyse how the interconnect architecture effects the shape of pre-routed cores and the wire bandwidth available to interfaces. We have adapted academic placement and routing algorithms to our architectural model. The design flow has been modified to include a wire policy and interface constraints framework that tightly constrains the use of the wires that cross a core’s boundaries. Using this tool set we investigate the effect of pre-routing on overall system optimality. Compiling a set of example systems using the pre-routed approach shows only a 2% increase in total wire use over the pre-placed approach. Place and route times are vastly reduced for systems composed of regular modules. Being able to break a system into independent cores reduces the placement and routing time even for non-regular systems, and will open opportunities for its possible use in resource constrained embedded systems.

BibTeX - Entry

  author =	{Maskell, Douglas and Oliver, Timothy F.},
  title =	{{Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--10},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{},
  URN =		{urn:nbn:de:0030-drops-7410},
  doi =		{10.4230/DagSemProc.06141.12},
  annote =	{Keywords: Dynamic Reconfiguration, Rapid Construction, FPGA Routing matrix}

Keywords: Dynamic Reconfiguration, Rapid Construction, FPGA Routing matrix
Collection: 06141 - Dynamically Reconfigurable Architectures
Issue Date: 2006
Date of publication: 09.10.2006

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