License: Creative Commons Attribution 3.0 Unported license (CC BY 3.0)
When quoting this document, please refer to the following
DOI: 10.4230/LIPIcs.DISC.2017.28
URN: urn:nbn:de:0030-drops-79811
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Issa, Shady ; Felber, Pascal ; Matveev, Alexander ; Romano, Paolo

Extending Hardware Transactional Memory Capacity via Rollback-Only Transactions and Suspend/Resume

LIPIcs-DISC-2017-28.pdf (0.6 MB)


Transactional memory (TM) aims at simplifying concurrent programming via the familiar abstraction of atomic transactions. Recently, Intel and IBM have integrated hardware based TM (HTM) implementations in commodity processors, paving the way for the mainstream adoption of the TM paradigm. Yet, existing HTM implementations suffer from a crucial limitation, which hampers the adoption of HTM as a general technique for regulating concurrent access to shared memory: the inability to execute transactions whose working sets exceed the capacity of CPU caches. In this paper we propose P8TM, a novel approach that mitigates this limitation on IBM's POWER8 architecture by leveraging a key combination of techniques: uninstrumented read-only transactions, Rollback Only Transaction-based update transactions, HTM-friendly (software-based) read-set tracking, and self-tuning. P8TM can dynamically switch between different execution modes to best adapt to the nature of the transactions and the experienced abort patterns. In-depth evaluation with several benchmarks indicates that P8TM can achieve striking performance gains in workloads that stress the capacity limitations of HTM, while achieving performance on par with HTM even in unfavourable workloads.

BibTeX - Entry

  author =	{Shady Issa and Pascal Felber and Alexander Matveev and Paolo Romano},
  title =	{{Extending Hardware Transactional Memory Capacity via Rollback-Only Transactions and Suspend/Resume}},
  booktitle =	{31st International Symposium on Distributed Computing (DISC 2017)},
  pages =	{28:1--28:16},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-053-8},
  ISSN =	{1868-8969},
  year =	{2017},
  volume =	{91},
  editor =	{Andr{\'e}a W. Richa},
  publisher =	{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{},
  URN =		{urn:nbn:de:0030-drops-79811},
  doi =		{10.4230/LIPIcs.DISC.2017.28},
  annote =	{Keywords: hardware transactional memory, self tuning, parallel programming}

Keywords: hardware transactional memory, self tuning, parallel programming
Collection: 31st International Symposium on Distributed Computing (DISC 2017)
Issue Date: 2017
Date of publication: 12.10.2017

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