License: Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported license (CC BY-NC-ND 3.0)
When quoting this document, please refer to the following
DOI: 10.4230/OASIcs.WCET.2005.813
URN: urn:nbn:de:0030-drops-8130
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2007/813/
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Stachulat, Jan ; Schliecker, Simon ; Ivers, Matthias ; Ernst, Rolf

Analysis of Memory Latencies in Multi-Processor Systems

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WCET_05.Ernst.813.pdf (0.3 MB)

Abstract

Predicting timing behavior is key to efficient embedded
real-time system design and verification. Current approaches
to determine end-to-end latencies in parallel heterogeneous
architectures focus on performance analysis either
on task or system level. Especially memory accesses,
basic operations of embedded application, cannot be accurately
captured on a single level alone: While task level
methods simplify system behavior, system level methods
simplify task behavior. Both perspectives lead to overly pessimistic
estimations.
To tackle these complex interactions we integrate task
and system level analysis. Each analysis level is provided
with the necessary data to allow precise computations,
while adequate abstraction prevents high time complexity.

BibTeX - Entry

@InProceedings{stachulat_et_al:OASIcs:2007:813,
  author =	{Jan Stachulat and Simon Schliecker and Matthias Ivers and Rolf Ernst},
  title =	{{Analysis of Memory Latencies in Multi-Processor Systems}},
  booktitle =	{5th International Workshop on Worst-Case Execution Time Analysis (WCET'05)},
  series =	{OpenAccess Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-24-8},
  ISSN =	{2190-6807},
  year =	{2007},
  volume =	{1},
  editor =	{Reinhard Wilhelm},
  publisher =	{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{http://drops.dagstuhl.de/opus/volltexte/2007/813},
  URN =		{urn:nbn:de:0030-drops-8130},
  doi =		{10.4230/OASIcs.WCET.2005.813},
  annote =	{Keywords: Multi-processor Performance Analysis, Memory Access Latency, Worst Case Execution Time}
}

Keywords: Multi-processor Performance Analysis, Memory Access Latency, Worst Case Execution Time
Collection: 5th International Workshop on Worst-Case Execution Time Analysis (WCET'05)
Issue Date: 2007
Date of publication: 29.03.2007

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