| No. | Title | Author | Year |
|---|---|---|---|
| 1 | Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs | Restuccia, Francesco et al. | 2020 |
| 2 | Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact) | Restuccia, Francesco et al. | 2020 |
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| Number of result pages: | 1 |
| Number of documents: | 2 |