License: 
Creative Commons Attribution 3.0 Unported license (CC BY 3.0)
When quoting this document, please refer to the following
DOI: 10.4230/DARTS.6.1.4
URN: urn:nbn:de:0030-drops-123941
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2020/12394/
Restuccia, Francesco ;
Pagani, Marco ;
Biondi, Alessandro ;
Marinoni, Mauro ;
Buttazzo, Giorgio
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact)
Abstract
This artifact provides the means for reproducing the experiments presented in the paper "Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoC". In particular, it provides the means and describes how to replicate the experimental study that has been carried out to evaluate the proposed analysis with synthetic workloads.
BibTeX - Entry
@Article{restuccia_et_al:DARTS:2020:12394,
author = {Francesco Restuccia and Marco Pagani and Alessandro Biondi and Mauro Marinoni and Giorgio Buttazzo},
title = {{Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact)}},
pages = {4:1--4:3},
journal = {Dagstuhl Artifacts Series},
ISSN = {2509-8195},
year = {2020},
volume = {6},
number = {1},
publisher = {Schloss Dagstuhl--Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/opus/volltexte/2020/12394},
URN = {urn:nbn:de:0030-drops-123941},
doi = {10.4230/DARTS.6.1.4},
annote = {Keywords: Heterogeneous computing, Predictable hardware acceleration, FPGA SoCs, Multi-Master architectures}
}
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Keywords: |
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Heterogeneous computing, Predictable hardware acceleration, FPGA SoCs, Multi-Master architectures |
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Collection: |
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DARTS, Volume 6, Issue 1, Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020) |
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Related Scholarly Article: |
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https://doi.org/10.4230/LIPIcs.ECRTS.2020.12 |
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Issue Date: |
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2020 |
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Date of publication: |
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30.06.2020 |
