License: Creative Commons Attribution 4.0 International license (CC BY 4.0)
When quoting this document, please refer to the following
DOI: 10.4230/LIPIcs.ECRTS.2021.1
URN: urn:nbn:de:0030-drops-139323
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2021/13932/
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Platzer, Michael ; Puschner, Peter

Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation

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LIPIcs-ECRTS-2021-1.pdf (0.8 MB)

Abstract

In this work, we present Vicuna, a timing-predictable vector coprocessor. A vector processor can be scaled to satisfy the performance requirements of massively parallel computation tasks, yet its timing behavior can remain simple enough to be efficiently analyzable. Therefore, vector processors are promising for highly parallel real-time applications, such as advanced driver assistance systems and autonomous vehicles. Vicuna has been specifically tailored to address the needs of real-time applications. It features predictable and repeatable timing behavior and is free of timing anomalies, thus enabling effective and tight worst-case execution time (WCET) analysis while retaining the performance and efficiency commonly seen in other vector processors. We demonstrate our architecture’s predictability, scalability, and performance by running a set of benchmark applications on several configurations of Vicuna synthesized on a Xilinx 7 Series FPGA with a peak performance of over 10 billion 8-bit operations per second, which is in line with existing non-predictable soft vector-processing architectures.

BibTeX - Entry

@InProceedings{platzer_et_al:LIPIcs.ECRTS.2021.1,
  author =	{Platzer, Michael and Puschner, Peter},
  title =	{{Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation}},
  booktitle =	{33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)},
  pages =	{1:1--1:18},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-192-4},
  ISSN =	{1868-8969},
  year =	{2021},
  volume =	{196},
  editor =	{Brandenburg, Bj\"{o}rn B.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/opus/volltexte/2021/13932},
  URN =		{urn:nbn:de:0030-drops-139323},
  doi =		{10.4230/LIPIcs.ECRTS.2021.1},
  annote =	{Keywords: Real-time Systems, Vector Processors, RISC-V}
}

Keywords: Real-time Systems, Vector Processors, RISC-V
Collection: 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)
Issue Date: 2021
Date of publication: 30.06.2021
Supplementary Material: Software: https://github.com/vproc/vicuna

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