License: Creative Commons Attribution 4.0 International license (CC BY 4.0)
When quoting this document, please refer to the following
DOI: 10.4230/OASIcs.WCET.2023.2
URN: urn:nbn:de:0030-drops-184319
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2023/18431/
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Gruin, Alban ; Carle, Thomas ; Rochange, Christine ; Sainrat, Pascal

Validation of Processor Timing Models Using Cycle-Accurate Timing Simulators

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OASIcs-WCET-2023-2.pdf (0.7 MB)

Abstract

We propose a workflow to help find errors in the processor models that are used to prove their timing predictability. Recently, several papers have modeled processor cores using formal models that represent how instructions progress through the pipeline in each execution cycle. However, such models grow with the complexity of the cores and they are built by hand, using a description of the core, usually the HDL-level code. Such a task is error-prone, and verifying that the model actually captures the core’s timing behavior is required, otherwise the proofs become useless. Our workflow simulates the execution of benchmark applications using the HDL specification of a core in order to extract timing information as well as other relevant information (e.g. cache miss events, branch mispredictions). This information is used to replay the execution in a simulator of the core timing model, and to determine whether or not the model accurately represents the execution timing of the instructions. To avoid writing the simulator by hand for each new core, or new variation of a core, we developed a compiler that translates the timing model of a core into a C++ program. We evaluated our approach on the open source MINOTAuR core and we show how it enabled us to detect and correct errors in its model.

BibTeX - Entry

@InProceedings{gruin_et_al:OASIcs.WCET.2023.2,
  author =	{Gruin, Alban and Carle, Thomas and Rochange, Christine and Sainrat, Pascal},
  title =	{{Validation of Processor Timing Models Using Cycle-Accurate Timing Simulators}},
  booktitle =	{21th International Workshop on Worst-Case Execution Time Analysis (WCET 2023)},
  pages =	{2:1--2:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-293-8},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{114},
  editor =	{W\"{a}gemann, Peter},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/opus/volltexte/2023/18431},
  URN =		{urn:nbn:de:0030-drops-184319},
  doi =		{10.4230/OASIcs.WCET.2023.2},
  annote =	{Keywords: Processor model, timing predictability, simulator generation}
}

Keywords: Processor model, timing predictability, simulator generation
Collection: 21th International Workshop on Worst-Case Execution Time Analysis (WCET 2023)
Issue Date: 2023
Date of publication: 26.07.2023

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