License: Creative Commons Attribution 3.0 Unported license (CC BY 3.0)
When quoting this document, please refer to the following
DOI: 10.4230/OASIcs.WCET.2014.53
URN: urn:nbn:de:0030-drops-46047
URL: http://dagstuhl.sunsite.rwth-aachen.de/volltexte/2014/4604/
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Schoeberl, Martin ; Chong, David Vh ; Puffitsch, Wolfgang ; Sparsø, Jens

A Time-Predictable Memory Network-on-Chip

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Abstract

To derive safe bounds on worst-case execution times (WCETs), all components of a computer system need to be time-predictable: the processor pipeline, the caches, the memory controller, and memory arbitration on a multicore processor. This paper presents a solution for time-predictable memory arbitration and access for chip-multiprocessors. The memory network-on-chip is organized as a tree with time-division multiplexing (TDM) of accesses to the shared memory. The TDM based arbitration completely decouples processor cores and allows WCET analysis of the memory accesses on individual cores without considering the tasks on the other cores. Furthermore, we perform local, distributed arbitration according to the global TDM schedule. This solution avoids a central arbiter and scales to a large number of processors.

BibTeX - Entry

@InProceedings{schoeberl_et_al:OASIcs:2014:4604,
  author =	{Martin Schoeberl and David Vh Chong and Wolfgang Puffitsch and Jens Spars\o},
  title =	{{A Time-Predictable Memory Network-on-Chip}},
  booktitle =	{14th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{53--62},
  series =	{OpenAccess Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-69-9},
  ISSN =	{2190-6807},
  year =	{2014},
  volume =	{39},
  editor =	{Heiko Falk},
  publisher =	{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{http://drops.dagstuhl.de/opus/volltexte/2014/4604},
  URN =		{urn:nbn:de:0030-drops-46047},
  doi =		{10.4230/OASIcs.WCET.2014.53},
  annote =	{Keywords: Real-Time Systems, Time-predictable Computer Architecture, Network-on-Chip, Memory Arbitration}
}

Keywords: Real-Time Systems, Time-predictable Computer Architecture, Network-on-Chip, Memory Arbitration
Collection: 14th International Workshop on Worst-Case Execution Time Analysis
Issue Date: 2014
Date of publication: 08.07.2014

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